An electronic system typically employs conductive traces, or nets, to carry electrical signals between the elements thereof. For example, an integrated circuit die includes nets to carry signals between its integrated electronic devices, and an integrated circuit package substrate includes nets to carry signals between an integrated circuit die and other components coupled to a motherboard. A motherboard, in turn, includes nets for carrying electrical signals between the components coupled thereto.
Nets which terminate at a component, a power supply or ground are commonly known as non-floating nets. In contrast, floating nets comprise conductive traces or other conductive structures that are not thusly coupled. Floating nets may comprise metal fill deposited in and/or on a substrate in order to provide desired mechanical properties (e.g., integrity, layer planarity, stiffness, strength, etc.). Floating nets may also comprise other uncoupled conductors or artifacts of a manufacturing process.
Floating and non-floating nets of an electronic system are typically taken into account during simulations or other studies of the system. For example, a system designer may consider the effects of mutual capacitances among floating and non-floating nets when analyzing the performance of an electronic system. According to some system analysis techniques, the above-described mutual capacitances as well as the ground capacitance of each net are used to generate a network of capacitors. The capacitor network is then converted to a “reduced” capacitor network that does not include mutual or ground capacitances associated with floating nets. The reduced capacitor network may be used to conduct various studies, including but not limited to timing studies.
According to one technique for reducing such a capacitor network, a capacitance matrix is determined that associates each non-floating net with each other non-floating net. The capacitance matrix takes into account mutual capacitances between each floating net and each non-floating net, as well as mutual capacitances between each floating net and each other floating net. As is known in the art, the sum of all capacitances in a row of the capacitance matrix is equal to a ground capacitance of a non-floating net associated with the row. Each capacitance in the row (except for the self-capacitance located on the leading diagonal) is equal to a mutual capacitance between the associated non-floating net and another non-floating net. The capacitance matrix may therefore be used to create a reduced network including capacitors between each non-floating net and ground (i.e., ground capacitors), and capacitors between each non-floating net and each other non-floating net. However, this capacitor network reduction technique is particularly resource-consuming if the system under analysis includes a large number of non-floating nets.
Some network reduction techniques are designed to specifically deal with large numbers of non-floating nets. According to some of these techniques, a mutual capacitance between a non-floating net and a floating net is converted to a capacitor between the non-floating net and ground, with the capacitor having a value equal to the mutual capacitance multiplied by a “decoupling factor” (e.g., 0.5). Mutual capacitances between floating nets, on the other hand, are ignored and therefore do not impact the reduced capacitor network resulting from these techniques. The resulting reduced capacitor network can be unsuitably inaccurate for some uses.